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SHIFT REGISTERDescription: This allows you to move a given composition (DATA_IN) to each pulse on CLK_IN. (paraginabile a shift register used in electronics) Note: For each pulse on the data on CLK_IN DATA_IN (numerical value) flows from D0 to D7. DATA_OUT presents the data on the eighth pulse CLK_IN to Uras in series in modules. COUNT_OUT value ranging from 1 to 8 (on the pulse CLK_IN) CICLO_OUT assumed value is TRUE when COUNT_OUT 8 For each pulse on ENABLE_OUT stored data is presented in output D0 to D7 - TRUE if kept in a data travels to each pulse on CLK_OUT RESET_OUT reset output data D0 D7, TRUE if the data is not maintained in transit.
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WTF!?
I like doing a bit of logic gate modelling in QC but I think a demo patch showing how and why one would use this marco would help a mere novice such as myself.